1. Field of the Invention
The present invention relates to negative step-up charge pump circuits that negatively step up an input voltage to produce a desired output voltage, and to LCD driver ICs and liquid crystal display devices incorporating such negative step-up charge pump circuits.
2. Description of Related Art
Conventionally, charge pump circuits are known that produce a desired output voltage by positively or negatively stepping up an input voltage through a plurality of stages of step-up units built with charge transfer transistors and charge transfer capacitors.
In the conventional charge pump circuits described above, field effect transistors are usually used as the charge transfer transistors, and their channel types are uniformly provided as either an N channel type or a P channel type throughout all the stages.
As an example of conventional technology related to the present invention, JP-A-H8-103070 (hereinafter “Patent Document 1”) discloses and proposes charge pump circuits whose substrate potential is mutually different between transistors forming, of a plurality of stages of step-up units, former-stage step-up units and transistors forming later-stage step-up units.
As another example of conventional technology related to the invention, JP-A-2003-197793 (hereinafter “Patent Document 2”, see FIG. 7 in particular) discloses and proposes charge pump circuits having four charge transfer transistors, those of which in the former stage are N channel types and the other of which in the later-stage are P channel types, and each of which has a drain and a substrate so connected as to be at the same potential.
With the conventional charge pump circuits described above, unlike a case where a switching regulator (chopper type regulator) is used, a desired step-up voltage can be produced without requiring a harmonic noise shield and an external coil.
However, as described above, with the conventional configuration in which the charge transfer transistors are uniformly provided as an N channel type or a P channel type throughout all the stages, there is an upper limit of the number of step-up stages upon formation of negative step-up charge pump circuits, thus resulting in risk of failure to produce a desired output voltage, for the following reasons.
Specifically, with the conventional configuration in which the charge transfer transistors are all provided as N channel types, when each of the transistors is formed by a process involving a single well alone, back gate potentials cannot be separated individually, which inevitably leads to necessity to set the back gate potentials of all the transistors at the minimum potential of the system (output potential of negative polarity). Therefore, a more former-stage transistor demonstrates tendency that its source potential and back gate potential differ from each other, and thus the more former-stage transistor is more likely to have difficulty in transition to the ON-state by back gate effect. Thus, for the conventional charge pump circuits described above, from a viewpoint of preventing start up failure, the number of the step-up units cannot be increased thoughtlessly.
On the other hand, with the conventional configuration in which the charge transfer transistors are all provided as P channel types, the minimum potential of the system (output potential of negative polarity) is applied as the gate potential of each transistor, and thus a more later-stage transistor demonstrates tendency that its potential between the gate and the source decreases and thus its current driving performance deteriorates. Thus, in the conventional charge pump circuits, from a viewpoint of maintaining desired current driving performance, the number of its step-up units cannot be increased thoughtlessly. It is possible to provide configuration in which a more later-stage transistor is sized larger to maintain the desired current driving performance, but this configuration is extremely inefficient in terms of chip area and thus fails to serve as practical solution.
The conventional technology of patent document 1 provides configuration which solve the problem described above by electrically separating the former-stage transistors and the later-stage transistors from each other to provide different potentials as back gate potentials of the respective transistors. Thus, this technology involves complication of processes and thus is essentially different from the invention of the application.
With the conventional technology of patent document 2, as indicated in FIG. 7 of this document and also its description, power sources and GND side input voltages of level shift circuits S1 to S4 are selected so that a value of the voltage Vgb between the gate and substrate of transistors M1 to M4 becomes equal to that of voltage Vgd between the gate and the drain, thereby complicating the circuits.